RTL寄存器传输级
Register-transfer level (RTL) is a hardware design abstraction that describes a digital circuit in terms of registers, data transfers, and the combinational logic operations performed along those paths in each clock cycle. In semiconductor localization, the term occurs in design specifications, synthesis scripts, verification plans, sign-off reviews, and IP core user guides, often alongside Verilog or VHDL source code, before gate-level or physical implementation is produced.
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Where this term appears
In translation and localization, RTL appears in front-end design documents, IP core integration guides, verification environment descriptions, and EDA tool reports. Translators may encounter it when localizing comments in Verilog or VHDL source files, synthesis constraints, or coverage reports. A recurring challenge is distinguishing this hardware abstraction from 'right-to-left' language direction, which often appears in UI and documentation localization.
Translation checks
A frequent translation error is expanding RTL as 'real-time logic' or 'right-to-left' in hardware documents. This causes serious confusion in verification and synthesis contexts, where RTL specifically denotes the register-transfer level source. Another error is translating 'RTL signoff' as if it were a legal approval step; it is a design readiness milestone, and using compliance language can misrepresent the engineering workflow.
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Related document experience
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Japanese → ChineseJapanese-to-Chinese documentation for a listed Japanese semiconductor manufacturer.
Read the published project →
SMIC (Semiconductor Manufacturing International)
English ⇄ ChineseCorporate reporting and disclosure documentation, delivered across successive annual cycles.
Read the published project →Published scope shows related industry experience; it does not confirm that this specific term was used or reviewed in the project.
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