Netlist网表
A netlist is a structured representation of a digital or analog circuit that lists its components, ports, and the electrical connections, or nets, between them in a format readable by electronic design automation tools. In chip design documentation, the netlist appears after schematic capture or logic synthesis and serves as input to simulation, verification, timing analysis, floorplanning, placement, routing, and layout-versus-schematic checks.
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Where this term appears
Netlist appears in translation of RTL-to-GDSII flow documentation, IP integration guides, sign-off checklists, EDA tool reports, and design review records. Translators encounter gate-level netlist, SPICE netlist, and netlist extraction. The main task is keeping net names, instance names, and tool commands unchanged while translating surrounding descriptions and warnings for engineers.
Translation checks
A common error is treating netlist as a simple 'component list' and dropping the connection information, which is the core of the term. Translators also sometimes localize net or instance names, but these identifiers must remain unchanged; otherwise the translated netlist can no longer be read by simulation or place-and-route tools.
Keep the term aligned across your files
Technical terms need checking against the source, approved product terminology and related specifications. Keep units, parameter conditions and document versions aligned across the file set.
Provide approved terms and previous translations with the source files. Agree how variants, ambiguous wording and revisions will be reviewed. Terminology maintenance and any termbase handback are confirmed in the project scope. See the 8-step AI + expert workflow.
Related document experience
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SMIC (Semiconductor Manufacturing International)
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Read the published project →Published scope shows related industry experience; it does not confirm that this specific term was used or reviewed in the project.
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