FinFET鳍式场效应晶体管
A FinFET is a three-dimensional transistor structure in which the gate wraps around a thin vertical silicon fin, providing better control of the channel than a planar transistor at reduced supply voltages. In advanced-node documentation, the term appears in process technology descriptions, PDK files, digital and mixed-signal standard cell libraries, and articles on short-channel effects, leakage reduction, and performance scaling.
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Where this term appears
In localization work, FinFET appears in process node announcements, technology briefs, PDK documentation, standard cell datasheets, and academic or patent translations. It also occurs in EDA tool documentation for parasitic extraction, physical verification, and timing sign-off where compact device models must account for three-dimensional channel behavior and advanced-node process variation.
Translation checks
A frequent issue is translating FinFET as “fin field-effect transistor” with inconsistent use of “鳍片” or “鳍式,” or treating it as a generic transistor. Because FinFET denotes a specific architecture with different leakage, drive, and variability characteristics, inconsistent terminology in PDK or library documents can confuse engineers selecting models and corners.
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Related document experience
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Japanese → ChineseJapanese-to-Chinese documentation for a listed Japanese semiconductor manufacturer.
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SMIC (Semiconductor Manufacturing International)
English ⇄ ChineseCorporate reporting and disclosure documentation, delivered across successive annual cycles.
Read the published project →Published scope shows related industry experience; it does not confirm that this specific term was used or reviewed in the project.
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