Scan Chain扫描链
A scan chain is a serial structure formed by connecting flip-flops or latches into a shift register so test patterns can be loaded and results shifted out. In DFT documentation, scan chains replace normal functional paths during test mode, allowing automatic test equipment to observe and control internal state with a small number of pins.
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Where this term appears
The term occurs in ATPG user manuals, DFT insertion reports, and silicon bring-up documents. Translators handle scan chain length settings, chain order, stuck-at and transition fault messages, and debugging instructions that mention shifting patterns through scan chains. Terminology consistency in scan insertion menus and test reports is particularly important because engineers rely on chain names.
Translation checks
A common error is to translate as '扫描链路' in one tool and '扫描链' in another, or to use the same term for boundary scan TAP chains and internal scan chains. In test documentation this inconsistency obscures which chain is being loaded, which pins are involved, and what fault model applies.
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