Latch-up闩锁效应
Latch-up is a failure mechanism in CMOS circuits in which parasitic bipolar transistors create a low-impedance path between supply rails, causing excessive current flow that can damage the device or its package. In reliability and design guideline documents, the term appears in testing specifications, layout rules, guard-ring recommendations, and failure analysis reports that address immunity to voltage or current stress and prevent destructive overcurrent.
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Where this term appears
In localization projects, latch-up appears in ESD and latch-up test reports, reliability qualification documents, design rule manuals, I/O cell documentation, and automotive or industrial component specifications. It also occurs in failure analysis reports and application notes that describe overvoltage events, current injection, or layout practices for avoiding unwanted parasitic paths.
Translation checks
A frequent error is translating latch-up as “锁存” or “闭锁” and mixing it with the digital latch storage function. Since latch-up is a destructive parasitic condition, a literal or generic translation in test reports can suggest a normal logic state, reducing the urgency of a reliability failure or masking the need for layout redesign.
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Related document experience
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Japanese → ChineseJapanese-to-Chinese documentation for a listed Japanese semiconductor manufacturer.
Read the published project →
SMIC (Semiconductor Manufacturing International)
English ⇄ ChineseCorporate reporting and disclosure documentation, delivered across successive annual cycles.
Read the published project →Published scope shows related industry experience; it does not confirm that this specific term was used or reviewed in the project.
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